Altera Vhdl Pin Assignment Quartus

  1. March 1st, 2010, 02:36 AM#1
    Join Date
    Mar 2010
    Posts
    11
    Rep Power
    1

    Pin assignment in Quartus II

    Hi all,

    After my design is added to the project if I tried to assign the pins automatically using compile Design option or I/O assignment analysis option available under compile design tool is giving a critical warning stating that "No exact pin location assignment for 29 pins of 49 total pins". This is happening for all my designs. Only Data pins are getting allocated every time i tried.

    Although i can allocate them manually using pin planner, but I need the default or suggested pin allocations.

    Kindly help me
  2. March 1st, 2010, 02:43 AM#2
    Join Date
    Mar 2010
    Posts
    11
    Rep Power
    1

    Re: Pin assignment in Quartus II

    Forgot to mention the tool used. Quartus II

  3. Re: Pin assignment in Quartus II

    Hi,

    it is not clear to me what you try to achieve ? Do you have a board with an FPGA and want to assign your design ports to certain FPGA pins ? Can you post your <>.qsf file ?

    Kind regards

    GPK
    Originally Posted by laxmanvv
    Forgot to mention the tool used. Quartus II
  4. March 1st, 2010, 11:11 PM#4
    Join Date
    Apr 2009
    Location
    Penang, Malaysia
    Posts
    10
    Rep Power
    1

    Re: Pin assignment in Quartus II

    I believe if you want to let Quartus II do the pin assignments for you, you don't have to go to pin assignment. Just compile the project and finish routing. It should be able to assign the pins for you randomly.
  5. March 2nd, 2010, 12:36 AM#5
    Join Date
    Mar 2010
    Posts
    11
    Rep Power
    1

    Re: Pin assignment in Quartus II

    No its not allocating the pins even I just compiled the design. Just beacause it is not allocating I choose pin planner. I want the allocation without pin planner involvement.

  6. Re: Pin assignment in Quartus II

    You can allocate the pins in the HDL

    in SystemVerilog do:
    module a(
    (* chip_pin = "A13" *) input wire LVDS_RX,
    (* chip_pin = "A14" *) output reg LVDS_TX);
  7. March 2nd, 2010, 04:00 PM#7
    Join Date
    Apr 2009
    Location
    San Jose
    Posts
    56
    Rep Power
    1

    Re: Pin assignment in Quartus II

    Last edited by kito; March 2nd, 2010 at 04:19 PM.
    Laxmanv. I assume you want to compile your design and stop quartus from warning about assigned pin locations? Is this what your asking?

    Normally if your using a dev kit, do not let quartus do pin assigment. However if your on a new design, then just compile it and quartus fitter will assign pins. Then use back annote assignments command.
  8. March 2nd, 2010, 09:13 PM#8
    Join Date
    Apr 2009
    Location
    Penang, Malaysia
    Posts
    10
    Rep Power
    1

    Re: Pin assignment in Quartus II

    Yeah, what you need to do is let Quartus II handle the random pin assignments. I believe it is the same for Xilinx ISE. Then after that, go to pin output file (in txt format) to view the pin report that is assigned by Quartus II
  9. March 3rd, 2010, 09:44 PM#9
    Join Date
    Mar 2010
    Posts
    11
    Rep Power
    1

    Re: Pin assignment in Quartus II

    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

  10. Re: Pin assignment in Quartus II

    Hi,

    looks like that my post is missing.

    you can preserve the pin assignment choosen by Quartus. You have to back-annotade the assignment. You can do that in following way:

    Choose:

    Assignment -> Back-Annotate Assignments

    Stay with the default setting "Pin&device Assignment" and press ok.

    The assignments are now written into the QSF.

    Kind regards

    GPK
    Originally Posted by laxmanvv
    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

Similar Threads

  1. Replies: 3
    Last Post: February 5th, 2010, 07:50 PM
  2. Replies: 6
    Last Post: May 7th, 2009, 06:23 PM
  3. Pin assignment
    By brunokasimin in forum Quartus II and EDA Tools Discussion
    Replies: 6
    Last Post: September 9th, 2008, 07:00 AM
  4. Replies: 5
    Last Post: November 28th, 2007, 11:21 PM
  5. Assignment pin
    By shishko in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 1
    Last Post: August 1st, 2007, 03:32 PM

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •  

Forum Rules


We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.

In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is

A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere.

B: Is this a horrible idea?

IDE is Quartus II 10.1 Development kit is MAX II Development Board Language is VHDL

EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.

vhdlalteraquartus

Categories: 1

0 Replies to “Altera Vhdl Pin Assignment Quartus”

Leave a comment

L'indirizzo email non verrà pubblicato. I campi obbligatori sono contrassegnati *